As state-of-the-art computer systems and circuits evolve, there is a continuing need for higher performance bipolar junction transistors capable of operating at higher switching speeds, with increasing degrees of device integration, and with low rate of failure. There is also a continuing need to shrink or scale down device size to obtain improved device performance.
Various techniques for forming high performance bipolar junction transistors have been developed. One technique for forming a conventional bipolar junction transistor, as illustrated by FIG. 1, is described in an article entitled "Lamp-Heated Rapid Vapor Phase Doping Technology for 100-GHz Si Bipolar Transistors, IEEE BCTM, 11:1, p. 173. Referring now to FIG. 1, a conventional bipolar junction transistor includes opposing insulator-filled trenches for providing electrical isolation and a buried extrinsic collector region 112a. A buried intrinsic collector region 130a, base region 133 and emitter region 134a are also provided between the buried extrinsic collector region 112a and a face of the semiconductor substrate 110. A collector contact region 130 is also provided between the extrinsic collector region 112a and the face. An in-situ boron-doped polysilicon layer (IBDP) is provided as a base electrode in ohmic contact with the base region 133. An in-situ phosphorus-doped polysilicon layer (IPDP) is provided as an emitter electrode in ohmic contact with the emitter region 134a and an in-situ phosphorus-doped polysilicon layer (IPDP) is provided as a collector electrode in ohmic contact with the collector contact region 130. Tungsten contact layers are provided on the emitter, base and collector electrodes, as illustrated. Field oxide isolation regions 120 and an electrically insulating layer 127 define an active portion of the substrate 110 and provide electrical isolation/passivation, respectively. Collector, emitter and base contacts 140, 144 and 142 are also provided, respectively.
Unfortunately, the bipolar junction transistor of FIG. 1 may suffer from an excessive parasitic collector-substrate capacitance (C.sub.CS) which may be a result of the relatively large junction area between the highly doped extrinsic collector region 112a and the substrate 110. This excessive parasitic capacitance can limit the maximum operating speed of the bipolar junction transistor. In addition, because the illustrated bipolar junction transistor utilizes multiple layers of in-situ doped polysilicon as electrodes, the vertical topology of the transistor may be degraded and the complexity of the associated technology for processing the transistor may be increased.
Thus, notwithstanding this and other conventional bipolar junction transistors, there continues to be a need for high speed and highly integrated bipolar transistors with reduced parasitic capacitances, improved topology and reduced unit cell size.